The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2022
Filed:
Feb. 11, 2021
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Dong Uk Lee, Icheon-si, KR;
Hae Chang Yang, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); H01L 27/11556 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01); H01L 45/06 (2013.01); G11C 2213/75 (2013.01);
Abstract
A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.