The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Aug. 07, 2017
Applicant:

Sumco Corporation, Tokyo, JP;

Inventors:

Naoya Nonaka, Nagasaki, JP;

Tadashi Kawashima, Albuquerque, NM (US);

Katsuya Ookubo, Nagasaki, JP;

Assignee:

SUMCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); C30B 29/06 (2006.01); C23C 16/24 (2006.01); H01L 21/205 (2006.01); H01L 21/02 (2006.01); H01L 29/167 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2022 (2013.01); C23C 16/24 (2013.01); C30B 29/06 (2013.01); H01L 21/02381 (2013.01); H01L 21/20 (2013.01); H01L 21/205 (2013.01); H01L 29/167 (2013.01);
Abstract

An epitaxial silicon wafer includes: a silicon wafer doped with phosphorus as a dopant and having an electrical resistivity of less than 1.0 m Ω·cm; and an epitaxial film formed on the silicon wafer. The silicon wafer includes: a main surface to which a (100) plane is inclined; and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°30' to 0°55′ in any direction with respect to an axis perpendicular to the main surface. The epitaxial silicon wafer has at most 1/cmof a density of a hillock defect generated thereon.


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