The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Sep. 03, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Se-Hwan Park, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/26 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01); G11C 29/04 (2006.01); G06N 3/04 (2006.01); G11C 16/08 (2006.01); H01L 27/115 (2017.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G06N 3/04 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 29/04 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 27/115 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/14511 (2013.01);
Abstract

Nonvolatile memory device includes memory cell region including first metal pad, peripheral circuit region including second metal pad, memory cell array, input current generator, operation cell array and analog-to-digital converter. Peripheral circuit region is vertically connected by first and second metal pads. Memory cell array in memory cell region includes NAND strings storing multiplicand data, wherein first ends of NAND strings are connected to bitlines and second ends of NAND strings output multiplication bits corresponding to bitwise multiplication of multiplicand data stored in NAND strings and multiplier data loaded on bitlines. Input current generator generates input currents. Operation cell array in memory cell region includes switching transistors. Gate electrodes of switching transistors are connected to second ends of NAND strings. Switching transistors selectively sum input currents based on multiplication bits to provide output currents. Analog-to-digital converter converts output currents to digital values.


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