The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

May. 14, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hee-Woong Kang, Suwon-si, KR;

Dong-Hun Kwak, Hwaseong-si, KR;

Jun-Ho Seo, Hwaseong-si, KR;

Hee-Won Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G11C 8/12 (2006.01); G11C 16/08 (2006.01); G11C 11/408 (2006.01); G11C 11/4097 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/06 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 7/109 (2013.01); G11C 7/12 (2013.01); G11C 8/12 (2013.01); G11C 11/4082 (2013.01); G11C 11/4085 (2013.01); G11C 11/4097 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/06 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); G11C 16/3436 (2013.01); G11C 2207/2209 (2013.01);
Abstract

A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.


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