The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Jul. 04, 2017
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Hiroaki Sakaguchi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 7/00 (2006.01); G06K 9/62 (2022.01); G06N 3/04 (2006.01); G06F 17/15 (2006.01); G06V 10/94 (2022.01); G06N 3/063 (2006.01); G06V 10/44 (2022.01);
U.S. Cl.
CPC ...
G06N 7/00 (2013.01); G06F 17/153 (2013.01); G06K 9/6232 (2013.01); G06K 9/6273 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06V 10/454 (2022.01); G06V 10/955 (2022.01);
Abstract

Parallel processing suitable for convolution operation in a convolutional neural network is executed. Each of a plurality of selectors sequentially selects data, which is held in a two-dimensional shift register, in predetermined two-dimensional regions at least partially different from each other. Each of a plurality of two-dimensional convolution operation circuits multiplies the data selected by the corresponding selector by coefficient data stored in a coefficient memory and accumulates results of the multiplication to calculate, in parallel, two-dimensional convolution operation results in the two-dimensional regions. Each of a plurality of adder circuits adds operation results of the two-dimensional convolution operation circuits in a channel direction to output a three-dimensional convolution operation result.


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