The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2022
Filed:
Sep. 18, 2020
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Krishna Teja Malladi, San Jose, CA (US);
Byung Hee Choi, Fremont, CA (US);
Andrew Chang, Los Altos, CA (US);
Ehsan M. Najafabadi, San Jose, CA (US);
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 15/173 (2006.01); G06F 9/4401 (2018.01); G06F 3/06 (2006.01); G06F 12/0808 (2016.01); G06F 12/1045 (2016.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 12/0802 (2016.01); G06F 13/28 (2006.01); H04L 49/45 (2022.01); H04L 49/351 (2022.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 3/0604 (2013.01); G06F 3/067 (2013.01); G06F 3/0619 (2013.01); G06F 3/0625 (2013.01); G06F 3/0629 (2013.01); G06F 3/0647 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 9/4401 (2013.01); G06F 12/0802 (2013.01); G06F 12/0808 (2013.01); G06F 12/1045 (2013.01); G06F 13/1663 (2013.01); G06F 13/28 (2013.01); G06F 13/409 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); G06F 15/17331 (2013.01); H04L 49/45 (2013.01); G06F 2212/621 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/28 (2013.01); H04L 49/351 (2013.01);
Abstract
A system and method for managing memory resources. In some embodiments, the system includes a first memory server, a second memory server, and a server-linking switch connected to the first memory server and to the second memory server. The first server may include a cache-coherent switch and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, and the cache-coherent switch is connected to the server-linking switch.