The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Jan. 15, 2021
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Katsuya Mizumoto, Tokyo, JP;

Toshiyuki Hiraki, Tokyo, JP;

Nobuhiko Honda, Tokyo, JP;

Sho Yamanaka, Tokyo, JP;

Takahiro Irita, Tokyo, JP;

Yoshihiko Hotta, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/362 (2006.01); G06F 13/18 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 13/1605 (2013.01); G06F 13/1689 (2013.01); G06F 13/18 (2013.01); G06F 13/362 (2013.01);
Abstract

Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.


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