The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2022

Filed:

Apr. 19, 2018
Applicant:

Arm Limited, Cambridge, GB;

Inventor:

Graeme Peter Barnes, Cambridge, GB;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/468 (2013.01); G06F 9/3861 (2013.01); G06F 9/4812 (2013.01); G06F 2209/481 (2013.01);
Abstract

An apparatus and method are provided for managing use of capabilities. The apparatus has processing circuitry to execute instructions, and a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain operations performed by the processing circuitry when executing instructions. The processing circuitry is operable at a plurality of exception levels, each exception level having different software execution privilege. Further, capability configuration storage is provided to identify capability configuration information for each of the plurality of exception levels. For each exception level, the capability configuration information identifies at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by capabilities. During a switch operation from a source exception level to a target exception level, the capability configuration information in the capability configuration storage pertaining to at least one of the source exception level and the destination exception level is used to determine how execution state of the processing circuitry is managed during the switch operation. This provides a great deal of flexibility in the management of capabilities.


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