The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Sep. 27, 2019
Applicant:

Zte Corporation, Guangdong, CN;

Inventors:

Changgang Yin, Guangdong, CN;

Yingxin Wang, Guangdong, CN;

Bi Yi, Guangdong, CN;

Huazhang Cao, Guangdong, CN;

Assignee:

ZTE CORPORATION, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/10 (2006.01); H05K 3/36 (2006.01); H05K 3/40 (2006.01); H05K 3/42 (2006.01); H05K 3/44 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/66 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0251 (2013.01); H05K 3/0094 (2013.01); H05K 3/429 (2013.01); H05K 2201/0212 (2013.01); H05K 2201/095 (2013.01);
Abstract

Provided are a circuit board, an apparatus and a method for forming a via hole structure. A via hole structure formed on a main body () of a circuit board includes a hole () enclosed by a conductive layer in the main body (), the conductive layer constitutes a wall () of the hole (), and a dielectric filling layer (), which has a dielectric constant smaller than that of the main body (), is disposed between at least a portion of the wall () of the hole () and the main body (), so that the parasitic capacitance of a via hole is decreased, and the impedance of the via hole is increased to become closer to the impedance of a transmission line, thereby effectively improving impedance continuity of a system link.


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