The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Apr. 08, 2019
Applicant:

Korrus, Inc., Los Angeles, CA (US);

Inventors:

Phil Kearney, Fremont, CA (US);

Laszlo Takacs, Fremont, CA (US);

Michael Larson, Fremont, CA (US);

Artem Mishin, Fremont, CA (US);

Assignee:

KORRUS, INC., Los Angeles, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 3/54 (2006.01); H04L 25/49 (2006.01); H05B 47/185 (2020.01); H04L 25/02 (2006.01); G05B 15/02 (2006.01); H04L 12/66 (2006.01);
U.S. Cl.
CPC ...
H04B 3/54 (2013.01); G05B 15/02 (2013.01); H04L 12/66 (2013.01); H04L 25/02 (2013.01); H04L 25/4902 (2013.01); H05B 47/185 (2020.01); H04B 2203/5458 (2013.01); Y02B 20/40 (2013.01);
Abstract

A system comprising: a host device comprising at least, an electrical interface configured for connection to a powerline; a first releasable interface; a powerline communication module for transmitting and receiving information over the powerline; an intelligent module comprising at least, a second releasable interface interconnected to the first releasable interface; a digital processor; memory operatively connected to the processor and configured with instructions for causing the processor to receive and transmit information over the powerline through the powerline communication module.


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