The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

Feb. 26, 2021
Applicants:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Tsinghua University, Beijing, CN;

Inventors:

Han Xu, Beijing, CN;

Fei Qiao, Beijing, CN;

Miao Zheng, Hangzhou, CN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); G11C 11/4094 (2006.01); G11C 5/06 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); H03K 19/017 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 5/06 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); H03K 19/01742 (2013.01);
Abstract

A static random access memory SRAM unit and a related apparatus are provided, to reduce power consumption of an SRAM when the SRAM memory is accessed. The SRAM unit is located in an SRAM memory, and the SRAM memory includes an SRAM storage array including a plurality of SRAM units. The SRAM unit includes: a storage circuit, connected to each of a write circuit and a read circuit, and configured to store data; the write circuit, configured to write data into the storage circuit; and the read circuit, configured to: after a read enabling signal is valid, enable data on a read bit line connected to the SRAM unit to be the data stored in the storage circuit.


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