The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 27, 2022

Filed:

May. 06, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Atsushi Nakamura, Tokyo, JP;

Akihiro Yamamoto, Tokyo, JP;

Kazuaki Terashima, Tokyo, JP;

Manabu Koike, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 9/30 (2018.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0615 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/4812 (2013.01); G06F 9/524 (2013.01); G06F 12/0284 (2013.01); G06F 13/1684 (2013.01); G11C 11/4082 (2013.01);
Abstract

A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.


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