The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Nov. 24, 2020
Applicant:

Dsp Group Ltd., Herzliya, IL;

Inventor:

Sergey Anderson, Netanya, IL;

Assignee:

DSP Group Ltd., Herzliya, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/02 (2006.01); H03F 3/193 (2006.01); H03F 1/56 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0205 (2013.01); H03F 1/56 (2013.01); H03F 3/193 (2013.01); H03F 2200/225 (2013.01); H03F 2200/294 (2013.01);
Abstract

A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply a bias voltage to a third port of the inductor; and wherein the tuning circuit is configured to control a capacitance of the first varactor and a capacitance of the variable capacitor.


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