The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Dec. 11, 2020
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Fumiya Watanabe, Chigasaki, JP;

Masaru Koyanagi, Ota, JP;

Yutaka Shimizu, Yokohama, JP;

Yasuhiro Hirashima, Kawasaki, JP;

Kei Shiraishi, Kawasaki, JP;

Mikihiko Ito, Ota, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/08 (2006.01); G11C 16/32 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/32 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 16/10 (2013.01);
Abstract

In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.


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