The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Aug. 22, 2019
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

David Alexander Majnemer, Mountain View, CA (US);

Blake Alan Hechtman, Mountain View, CA (US);

Bjarke Hammersholt Roune, Mountain View, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G06N 3/08 (2006.01); G06N 3/04 (2006.01); G06N 3/10 (2006.01); G06F 17/15 (2006.01); G06F 17/16 (2006.01); G06F 30/18 (2020.01); G06F 30/20 (2020.01); G06F 30/27 (2020.01); G06F 30/367 (2020.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 17/15 (2013.01); G06F 17/16 (2013.01); G06F 30/18 (2020.01); G06F 30/20 (2020.01); G06F 30/27 (2020.01); G06F 30/367 (2020.01); G06N 3/0454 (2013.01); G06N 3/086 (2013.01); G06N 3/10 (2013.01);
Abstract

Methods and systems, including computer programs encoded on a computer storage medium. In one aspect, a method includes the actions of receiving a request to perform convolutional computations for a neural network on a hardware circuit having a matrix computation unit, the request specifying the convolutional computation to be performed on a feature tensor and a filter and padding applied to the feature tensor prior to performing the convolutional computation; and generating instructions that when executed by the hardware circuit cause the hardware circuit to perform operations comprising: transferring feature tensor data from a main memory of the hardware circuit to a scratchpad memory of the hardware circuit; and repeatedly performing the following operations: identifying a current subset of the feature tensor; and determining whether a memory view into the scratchpad memory for the current subset is consistent with a memory view of the current subset in the main memory.


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