The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Jul. 15, 2019
Applicant:

Hewlett-packard Development Company, L.p., Spring, TX (US);

Inventors:

Bartley Mark Hirst, Boise, ID (US);

Cody Ravenscroft, Boise, ID (US);

Charles Logan, Boise, ID (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/42 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 21/85 (2013.01);
U.S. Cl.
CPC ...
G06F 13/4291 (2013.01); G06F 13/385 (2013.01); G06F 13/4068 (2013.01); G06F 21/85 (2013.01);
Abstract

Aspects are directed to systems in which control node communicates through a peripheral-side wired communications bus for data communications with other bus-coupled nodes. The control node acts as a master with a main-circuit domain during an initialization mode and when the main-circuit domain is deactivated, and acts as a slave, after completion of the initialization mode and when the main-circuit domain is not deactivated. An isolation circuit is used to isolate the main-circuit domain from the control node and, while the main-circuit domain is deactivated, to facilitate communications over the peripheral-side wired communications bus between the control node and another node connected to the peripheral-side wired communications bus.


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