The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Feb. 02, 2021
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Chun-Yuan Yeh, Hsinchu, TW;

Yan-Bin Luo, Hsinchu, TW;

Tse-Hsiang Hsu, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/78 (2006.01); G06F 11/07 (2006.01); G06F 13/40 (2006.01); G06F 13/20 (2006.01); G06F 13/42 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 13/20 (2013.01); G06F 13/4208 (2013.01); G06F 13/4291 (2013.01); H01L 25/0655 (2013.01);
Abstract

A multi-package system includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first die and a second die. The second semiconductor package includes a third die. A first processing circuit of the first die communicates with a second processing circuit of the second die through a first configurable input/output (IO) interface circuit of the first die and a third configurable IO interface circuit of the second die that are configured to perform single-ended intra-package communication. The first processing circuit of the first die communicates with a third processing circuit of the third die through a second configurable IO interface circuit of the first die and a fourth configurable IO interface circuit of the third die that are configured to perform differential inter-package communication. The first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.


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