The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2022

Filed:

Sep. 11, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gregory J. Fredeman, Wappingers Falls, NY (US);

Glenn David Gilda, Binghamton, NY (US);

Thomas E. Miller, Poughkeepsie, NY (US);

Arthur O'Neill, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 12/0875 (2016.01); G06F 11/16 (2006.01); G11C 29/30 (2006.01); G06F 11/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2017 (2013.01); G06F 11/1064 (2013.01); G06F 11/1666 (2013.01); G06F 12/0875 (2013.01); G11C 29/30 (2013.01); G06F 2212/70 (2013.01); G11C 2029/0401 (2013.01);
Abstract

A computer-implemented method for memory macro disablement in a cache memory includes identifying a defective portion of a memory macro of a cache memory bank. The method includes iteratively testing each line of the memory macro, the testing including attempting at least one write operation at each line of the memory macro. The method further includes determining that an error occurred during the testing. The method further includes, in response to determining the memory macro as being defective, disabling write operations for a portion of the cache memory bank that includes the memory macro by generating a logical mask that includes at least bits comprising a compartment bit, and read address bits.


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