The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2022
Filed:
Jul. 31, 2016
Applicant:
Microsoft Technology Licensing, Llc, Redmond, WA (US);
Inventors:
Aaron L. Smith, Seattle, WA (US);
Jan S. Gray, Bellevue, WA (US);
Assignee:
Microsoft Technology Licensing, LLC, Redmond, WA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 15/78 (2006.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3836 (2013.01); G06F 9/3005 (2013.01); G06F 9/3016 (2013.01); G06F 9/3017 (2013.01); G06F 9/30181 (2013.01); G06F 9/30185 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/3834 (2013.01); G06F 9/3838 (2013.01); G06F 9/3855 (2013.01); G06F 9/3873 (2013.01); G06F 9/3885 (2013.01); G06F 9/3889 (2013.01); G06F 9/3897 (2013.01); G06F 12/0875 (2013.01); G06F 15/7867 (2013.01);
Abstract
Apparatus and methods are disclosed for implementing block-based processors having custom function blocks, including field-programmable gate array (FPGA) implementations. In some examples of the disclosed technology, a dynamically configurable scheduler is configured to issue at least one block-based processor instruction. A custom function block is configured to receive input operands for the instruction and generate ready state data indicating completion of a computation performed for the instruction by the respective custom function block.