The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2022
Filed:
Jul. 09, 2020
Neuralink Corp., Fremont, CA (US);
Supin Chen, San Ramon, CA (US);
Camilo A. Diaz-Botia, Monte Sereno, CA (US);
Dongjin Seo, San Francisco, CA (US);
Vanessa M. Tolosa, Emeryville, CA (US);
Neuralink Corp., Fremont, CA (US);
Abstract
Disclosed is a sandwich assembly containing a thin film electrode array for use with high density electrodes. To minimize the volume required by the associated electronics, the electrode array and integrated circuits are sandwiched over a Printed Circuit Board (PCB), which may have other integrated circuits on an opposite side. Among other things, the disclosed apparatus, system, and method improve over previous systems by providing holes and vias that facilitate communication between a custom chip above the PCB and a field-programmable gate array (FPGA) below. The thin film electrode array can be fastened by bucking a pillar of stacked gold or other metal balls to rivet the thin film flex circuit. The system can include a thin film array having embedded wire traces and holes, a PCB having vias aligned with the holes, chips including an analog-to-digital converter (ADC) sandwiching the thin film, and solder connections from the chips through the holes to the vias.