The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

May. 29, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Noriaki Oda, Yokkaichi, JP;

Teruo Okina, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/564 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.


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