The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

May. 15, 2020
Applicant:

Massachusetts Institute of Technology, Cambridge, MA (US);

Inventors:

Mordechai Rothschild, Newton, MA (US);

Sumanth Kaushik, Belmont, MA (US);

Melissa A. Smith, Cambridge, MA (US);

Livia Racz, Belmont, MA (US);

Dennis Burianek, Acton, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/48 (2006.01); H01L 21/78 (2006.01); G01S 19/37 (2010.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); G01S 19/37 (2013.01); H01L 21/78 (2013.01); H01L 23/481 (2013.01);
Abstract

A wafer-scale satellite bus and a manner of making the same include using wafer reconstruction techniques to stack functional diced circuits onto each other and bond them. The disclosed techniques allow for a variety of functions in each die, including providing, without limitation: ground-based communications, attitude and propulsion control, fuel tanks and thrusters, and power generation. The wafers are initially manufactured according to a common wafer design that provides electrical and power interconnects, then different wafers are further processed using subsystem-specific techniques. The circuits on differently-processed wafers are reconstructed into a single stack using e.g. wafer bonding. Surface components are mounted, and the circuitry is diced to form the final satellites. Mission-specific functions can be incorporated, illustratively by surface-mounting, to the bus at an appropriate stage of assembly, on-wafer circuitry or instrument packages for performing these functions.


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