The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Nov. 12, 2019
Applicant:

Tcl China Star Optoelectronics Technology Co., Ltd., Guangdong, CN;

Inventor:

Jinyang Zhao, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/71 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 21/20 (2006.01); H01L 21/77 (2017.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02686 (2013.01); H01L 21/02425 (2013.01); H01L 21/02491 (2013.01); H01L 21/02675 (2013.01); H01L 21/2026 (2013.01); H01L 21/76894 (2013.01); H01L 21/77 (2013.01); H01L 27/127 (2013.01); H01L 27/1237 (2013.01);
Abstract

The present invention provides a manufacturing method of an array substrate, including steps of: providing a flexible substrate layer, forming a buffer layer, forming an active layer, forming a gate insulating layer, forming a gate layer, forming an interlayer insulating layer, forming a source and drain layer, forming an organic planarization layer, forming an anode layer. An array substrate manufactured by the above manufacturing method, and the array substrate includes laminated a flexible substrate layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, an organic planarization layer, and an anode layer, which are disposed in a stack.


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