The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2022
Filed:
Apr. 18, 2018
Applicant:
Microchip Technology Incorporated, Chandler, AZ (US);
Inventors:
Lorenzo Bedarida, Vimercate, IT;
Simone Bartoli, lecco, IT;
Albert S. Weiner, Colorado Springs, CO (US);
Assignee:
Microchip Technology Incorporated, Chandler, AZ (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/02 (2006.01); G06F 13/28 (2006.01); G11C 8/10 (2006.01); G11C 16/08 (2006.01); G11C 7/24 (2006.01); G11C 8/20 (2006.01); G11C 29/44 (2006.01); G11C 29/38 (2006.01);
U.S. Cl.
CPC ...
G11C 29/024 (2013.01); G06F 13/28 (2013.01); G11C 7/24 (2013.01); G11C 8/10 (2013.01); G11C 8/20 (2013.01); G11C 16/08 (2013.01); G11C 29/02 (2013.01); G11C 29/44 (2013.01); G11C 29/38 (2013.01);
Abstract
A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.