The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2022
Filed:
Jan. 23, 2017
Applicant:
Samsung Display Co., Ltd., Yongin-si, KR;
Inventors:
Cholho Kim, Seoul, KR;
Gunwoo Yang, Seoul, KR;
Hyunyoung Choi, Seoul, KR;
Jihoon Yang, Seoul, KR;
Yongwoo Lee, Gimpo-si, KR;
Assignee:
SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); G09G 3/36 (2006.01); G09G 3/296 (2013.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G09G 3/296 (2013.01); G09G 3/3659 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0223 (2013.01);
Abstract
A gate driver according to an exemplary embodiment of the present inventive concept includes a pull-up-pull-down circuit configured to pull up a gate signal to a high level of a first clock signal in a first duration and configured to pull down the gate signal to a low level of the first clock signal in a second duration, and a pull-down boosting circuit configured to output a first off voltage to the pull-up-pull-down part in the second duration in response to a second clock signal.