The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

May. 18, 2020
Applicant:

Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;

Inventors:

Geun-Young Park, Milpitas, CA (US);

Seong-Jun Jang, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G11C 11/409 (2006.01); G11C 11/406 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1605 (2013.01); G11C 11/409 (2013.01); G11C 11/40615 (2013.01); H03K 19/20 (2013.01);
Abstract

An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a set-reset latch circuit receiving a normal access request signal and a refresh access request signal as first and second input signals and generating a first output signal having zero or more signal transitions in response to the order the first input signal and the second input signal is asserted. The arbitration control circuit further includes a unidirectional delay circuit applying a unidirectional delay to the first output signal and a D-flip-flop circuit latching the first output signal as data in response to the delayed signal as clock. The D-flip-flop generates a second output signal having a first logical state indicative of granting the normal access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.


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