The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Jun. 01, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Michael E. Peattie, Campbell, CA (US);

Niloy Roy, Hyderabad, IN;

Vishal Kumar Vangala, Hyderabad, IN;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/36 (2006.01); G06F 11/27 (2006.01); H04L 49/109 (2022.01); G01R 31/3185 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3656 (2013.01); G01R 31/318533 (2013.01); G06F 11/0751 (2013.01); G06F 11/27 (2013.01); H04L 49/109 (2013.01);
Abstract

An integrated circuit includes a high-speed interface configured to communicate with a host system for debugging and a debug hub coupled to the high-speed interface. The debug hub is configured to receive a debug command from the host system as memory mapped data. The integrated circuit also includes a plurality of debug cores coupled to the debug hub. Each debug core is coupled to the debug hub by channels. The debug hub is configured to translate the debug command to a data stream and provide the data stream to a target debug core of the plurality of debug cores based on an address specified by the debug command.


Find Patent Forward Citations

Loading…