The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2022
Filed:
Apr. 25, 2019
Invensense, Inc., San Jose, CA (US);
James Christian Salvia, San Jose, CA (US);
Michael H. Perrott, Nashua, NH (US);
Marian Voros, Bratislava, SK;
Eldwin Ng, Mountain View, CA (US);
Julius Ming-Lin Tsai, San Jose, CA (US);
Nikhil Apte, Palo Alto, CA (US);
InvenSense, Inc., San Jose, CA (US);
Abstract
An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array and a plurality of MEMS devices. Each CMOS control element of the plurality of CMOS control elements includes at least one of a low voltage semiconductor device, a high voltage PMOS semiconductor device, and a high voltage NMOS semiconductor device. Each MEMS device of the plurality of MEMS devices is associated with a CMOS control element of the plurality of CMOS control elements. The plurality of CMOS control elements are arranged in the two-dimensional array such that low voltage semiconductor devices are only adjacent to other low voltage semiconductor devices, high voltage PMOS semiconductor devices are only adjacent to other high voltage PMOS semiconductor devices, and high voltage NMOS semiconductor devices are only adjacent to other high voltage NMOS semiconductor devices.