The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2022

Filed:

Feb. 26, 2020
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Yizhen Lin, Schenectady, NY (US);

Marco Francesco Aimi, Niskayuna, NY (US);

Alessandro Stuart Savoia, Rome, IT;

Assignee:

GENERAL ELECTRIC COMPANY, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); B06B 1/02 (2006.01); B81B 3/00 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B06B 1/0292 (2013.01); B81B 3/0021 (2013.01); B81C 1/00357 (2013.01); B81B 2201/0271 (2013.01); B81B 2203/0127 (2013.01); B81B 2207/012 (2013.01); B81B 2207/07 (2013.01); B81C 2201/0125 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/0194 (2013.01); B81C 2203/0109 (2013.01); B81C 2203/0792 (2013.01);
Abstract

A method of forming a capacitive micromachined ultrasonic transducer (CMUT) device includes bonding a CMUT substrate to a silicon on insulator (SOI) substrate. The CMUT substrate has a first thickness and the SOI substrate includes a handle, a buried oxide layer, and a device layer. At least one of the CMUT substrate or the SOI substrate includes a patterned dielectric layer. The device layer is bonded to the patterned dielectric layer to form a plurality of sealed cavities and the device layer forms a diaphragm of the plurality of cavities. The method further includes reducing the first thickness of the CMUT substrate to a second thickness and forming a plurality of through-silicon vias from a second surface of the CMUT substrate opposite the first surface.


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