The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2022
Filed:
Nov. 06, 2020
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Junghoon Park, Gyeonggi-do, KR;
Seungbo Shim, Gyeonggi-do, KR;
Seunggoo Kang, Gyeonggi-do, KR;
Seockkeun Han, Gyeonggi-do, KR;
Dongil Son, Gyeonggi-do, KR;
Abstract
Provided is an electronic device. The electronic device may include a housing; a first printed circuit board (PCB) disposed in an internal space of the housing and including a plurality of first conductive terminals; a second PCB arranged parallel to the first PCB in the internal space, and including a plurality of second conductive terminals; and an interposer disposed between the first PCB and the second PCB to electrically connect the first PCB and the second PCB, the interposer including: a dielectric substrate including a first substrate surface facing the first PCB, a second substrate surface facing the second PCB, and a substrate side surface surrounding a space between the first substrate surface and the second substrate surface; a plurality of conductive vias formed to penetrate from the first substrate surface of the dielectric substrate to the second substrate surface, and electrically connecting the plurality of first conductive terminals to the plurality of second conductive terminals; and a first conductive pattern formed from at least a portion of the substrate side surface to the first PCB, wherein the first conductive pattern may be electrically connected to a first conductive pad formed on the first PCB and electrically connected to the at least one first electrical element.