The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Feb. 05, 2020
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Baal Yang, Santa Clara, CA (US);

Daniel Lin, Santa Clara, CA (US);

Sunil Sudhakaran, Santa Clara, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/14 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/116 (2013.01); H05K 1/0298 (2013.01); H05K 1/141 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/10734 (2013.01);
Abstract

This disclosure provides a multi-layered printed circuit board (PC) that has signal array region. The signal array region has a width and circumscribes a power core region and has signal vias connected to respective signal ball pads, and ground vias connected to respective ground ball pads within the signal array region that have an associated ball pad pitch. The PCB also has an inner current power layer. The signal and ground vias are arranged on the component layer in a pattern and extend into the inner current layer. The pattern forms current power paths across the width of the signal array region, such that the current power paths have a width that is at least about 50% as wide as the ball pad pitch.


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