The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2022
Filed:
Nov. 30, 2018
Applicant:
Rohm Co., Ltd., Kyoto, JP;
Inventors:
Yuji Ishimatsu, Kyoto, JP;
Ryuichi Furutani, Kyoto, JP;
Assignee:
ROHM CO, LTD., Kyoto, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 23/3107 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H01L 23/5227 (2013.01); H01L 24/06 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48139 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/182 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19105 (2013.01);
Abstract
A semiconductor device Aincludes a substrate, a conductive sectionformed on the substrateand including a conductive material, a leadA located on the substrate, a semiconductor chipA located on the leadA, a control chipG located on the substrateand electrically connected to the conductive sectionand the semiconductor chipA for controlling an operation of the semiconductor chipA, and a resincovering the semiconductor chipA, the control chipG, at least a part of the substrateand a part of the leadA. This configuration contributes to achieving a higher level of integration of the semiconductor device.