The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Nov. 12, 2020
Applicant:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Inventors:

Seom Geun Lee, Ansan-si, KR;

Seong Kyu Jang, Ansan-si, KR;

Yong Woo Ryu, Ansan-si, KR;

Jong Hyeon Chae, Ansan-si, KR;

Assignee:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/075 (2006.01); H01L 33/42 (2010.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 25/0756 (2013.01); H01L 25/0753 (2013.01); H01L 33/42 (2013.01); H01L 33/62 (2013.01);
Abstract

A light emitting device including a first LED stack, a second LED stack, and a third LED stack each including first and second conductivity type semiconductor layers, a first bonding layer between the second and third LED stacks, a second bonding layer between the first and second LED stacks, a first planarization layer between the second bonding layer and the second LED stack, a second planarization layer disposed on the first LED stack, lower buried vias passing through the first planarization layer, the second LED stack, and the first bonding layer and electrically connected to the semiconductor layers of the third LED stack, respectively, and upper buried vias passing through the second planarization layer and the first LED stack, in which a width of an upper end of each of the lower buried vias and the upper buried vias is greater than a width of a corresponding through hole.


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