The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Jun. 03, 2020
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Binhao Wang, Palo Alto, CA (US);

Wayne Victor Sorin, Palo Alto, CA (US);

Michael Renne Ty Tan, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 23/538 (2006.01); H01L 27/144 (2006.01); H01L 23/64 (2006.01); H04B 10/69 (2013.01); H04J 14/02 (2006.01); H04B 10/40 (2013.01);
U.S. Cl.
CPC ...
H01L 23/5385 (2013.01); H01L 23/5384 (2013.01); H01L 23/642 (2013.01); H01L 27/1443 (2013.01); H01L 27/1446 (2013.01); H04B 10/69 (2013.01); H04J 14/02 (2013.01); H04B 10/40 (2013.01);
Abstract

A silicon interposer may include an on-chip DC blocking capacitor, comprising: a first electrical connection to couple to a supply voltage and to cathodes of a plurality of photodiodes formed in a two-dimensional photodiode array on a first substrate, and a second electrical connection to couple to ground and to ground inputs of a plurality of transimpedance amplifiers on a second substrate; wherein the on-chip DC blocking capacitor is configured to be shared among a plurality of receiver circuits comprising the plurality of photodiodes and the plurality of transimpedance amplifiers; and wherein the silicon interposer comprises a substrate separate from the first substrate and the second substrate.


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