The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Feb. 27, 2019
Applicant:

Kyocera Corporation, Kyoto, JP;

Inventors:

Hiroshi Matsumoto, Kirishima, JP;

Hiroki Ito, Kirishima, JP;

Takashi Kimura, Kirishima, JP;

Assignee:

KYOCERA CORPORATION, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 23/14 (2006.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 23/047 (2006.01); H01L 23/08 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 21/4882 (2013.01); H01L 23/047 (2013.01); H01L 23/08 (2013.01); H01L 23/14 (2013.01); H01L 23/36 (2013.01); H01L 23/562 (2013.01);
Abstract

A semiconductor package in an aspect of the present invention includes a metal board, a first frame, a second frame, and a bond. The metal board has an upper surface including a mount on which a semiconductor device is mountable. The first frame has a side surface facing a side surface of the metal board and has a smaller thermal expansion coefficient than the metal board. The second frame is on upper surfaces of the metal board and the first frame and surrounds the mount, and has a smaller thermal expansion coefficient than the metal board. The bond is between the metal board and the first frame, between the metal board and the second frame, and between the first frame and the second frame. The semiconductor package includes an alloy layer between the metal board and the bond.


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