The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2022
Filed:
May. 01, 2018
Applicant:
Drexel University, Philadelphia, PA (US);
Inventors:
Ioannis Savidis, Wallingford, PA (US);
Divya Pathak, Philadelphia, PA (US);
Houman Homayoun, Fairfax, VA (US);
Assignee:
Drexel University, Philadelphia, PA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/28 (2006.01); G06F 9/50 (2006.01); G06F 1/329 (2019.01);
U.S. Cl.
CPC ...
G06F 1/28 (2013.01); G06F 1/329 (2013.01); G06F 9/5083 (2013.01);
Abstract
A real-time workload scheduling heuristic assigns tasks to the cores such that the total load current consumption of the cores is always less than the total current capability of the under-provisioned on-chip voltage regulators. In addition, the energy-efficient scheduling of the tasks on to the cores ensures that the reconfiguration of the power delivery network is minimized. The heuristic includes DVFS management based on the unique constraints of the under provisioned voltage regulators.