The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Nov. 21, 2019
Applicant:

Asml Netherlands B.v., Veldhoven, NL;

Inventor:

Marleen Kooiman, Eindhoven, NL;

Assignee:

ASML Netherlands B.V., Veldhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01); G01N 23/2251 (2018.01); H01J 37/26 (2006.01); H01J 37/285 (2006.01);
U.S. Cl.
CPC ...
G03F 7/70625 (2013.01); G01N 23/2251 (2013.01); G03F 7/7065 (2013.01); G03F 7/70616 (2013.01); H01J 37/265 (2013.01); H01J 37/285 (2013.01); G06T 2207/10061 (2013.01); G06T 2207/30148 (2013.01); G06T 2207/30168 (2013.01); H01J 2237/221 (2013.01); H01J 2237/2817 (2013.01);
Abstract

A method of reducing variability of an error associated with a structure on a substrate in a lithography process is disclosed. The method includes determining, based on one or more images obtained based on a scan of the substrate by a scanning electron microscope (SEM), a first error due to a SEM distortion in the image. The method also includes determining, based on the image, a second error associated with a real error of the structure, where the error associated with the structure includes the first error and the second error. A command is generated by a data processor that enables a modification of the lithography process and an associated reduction of the variability of the error based on reducing any of the first error or the second error.


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