The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 06, 2022

Filed:

Oct. 28, 2020
Applicant:

Allegro Microsystems, Llc, Manchester, NH (US);

Inventor:

Mathew Drouin, Hooksett, NH (US);

Assignee:

Allegro MicroSystems, LLC, Manchester, NH (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01D 5/22 (2006.01); H03L 7/099 (2006.01); H03K 5/00 (2006.01); G01D 18/00 (2006.01); G01R 33/12 (2006.01); H03L 7/093 (2006.01);
U.S. Cl.
CPC ...
G01D 5/225 (2013.01); G01D 18/00 (2013.01); G01R 33/12 (2013.01); H03K 5/00 (2013.01); H03L 7/093 (2013.01); H03L 7/099 (2013.01); H03K 2005/00013 (2013.01);
Abstract

An interface circuit for a position sensor system including an oscillator generating an oscillation signal having a carrier frequency and a primary phase, a primary coil responsive to the oscillation signal, and a secondary coil electromagnetically coupled to the primary coil by a target and configured to generate a secondary signal having the carrier frequency and a secondary phase provides phase compensation. The interface circuit includes a sampling and conversion circuit configured to sample the secondary signal during sample periods and convert the secondary signal into a digital signal, a demodulator coupled to receive the digital signal and configured to demodulate the digital signal in order to generate a position signal indicative of a position of the target, a phase detector coupled to receive the position signal and configured to detect an alignment of the secondary phase with respect to the sample periods and generate a phase detector output signal indicative of whether the secondary phase is aligned with the sample periods, and a delay circuit responsive to the phase detector output signal and configured to apply a delay to the sampling and conversion circuit if the phase detector output signal indicates that the secondary phase is not aligned with the sample periods.


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