The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Dec. 09, 2020
Applicant:

Technion Research & Development Foundation Limited, Haifa, IL;

Inventors:

Loai Danial, Nazareth, IL;

Shahar Kvatinsky, Hanaton, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/18 (2006.01); H03M 1/26 (2006.01); G06N 3/063 (2006.01); G06K 9/62 (2022.01); G06N 3/04 (2006.01); H03M 1/44 (2006.01);
U.S. Cl.
CPC ...
H03M 1/181 (2013.01); G06K 9/6256 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); H03M 1/26 (2013.01); H03M 1/44 (2013.01);
Abstract

A pipelined ADC system comprising: a first ADC stage comprising a trainable neural network layer and configured to receive an analog input signal, and convert it into a first n-bit digital output representing said analog input signal; a DAC circuit comprising a trainable neural network layer and configured to receive said first n-bit digital output, and convert it into an analog output signal representing said first n-bit digital output; and a second ADC stage comprising a trainable neural network layer and configured to receive a residue analog input signal of said analog input signal, and convert it into a second n-bit digital output representing said residue analog input signal; wherein said first and second n-bit digital outputs are combined to generate a combined digital output representing said analog input signal.


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