Capacitor structure and a chip antenna

Abstract

A capacitor structure implemented using a semiconductor process. The capacitor structure includes a plurality of interdigitated positive and negative electrode fingers separated by a dielectric material, and a plurality of patterned metallization layers separated by the dielectric material. Each interdigitated electrode finger comprises a lateral part formed on one of at least two essentially parallel first metallization layers and a vertical part includes a plurality of superimposed slabs or bars disposed on a plurality of second metallization layers between said first metallization layers and electrically connected to each other and to the lateral part with a plurality of electrically conducting vias traversing through dielectric material separating adjacent metallization layers. Vertical distance between each pair of at least partially superimposed lateral parts of two adjacent electrode fingers is substantially equal to lateral distance between two adjacent vertical parts.