The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Feb. 09, 2021
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Alexander Bazarsky, Holon, IL;

David Rozman, Kiryat Malakhi, IL;

Eran Sharon, Rishon Lezion, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); G11C 16/3436 (2013.01); G11C 2207/2254 (2013.01); G11C 2207/2281 (2013.01);
Abstract

Read reference levels are calibrated by calibrating integration times. An integration time is the length of time for which the charge on a sense node is allowed to change while the memory cell is being sensed. Calibrating the integration time is much faster than calibrating the reference voltage itself. This is due, in part, to reducing the number of different reference voltages that need to be applied during calibration. Calibrating the integration time may use different test integration times for a given read reference voltage, thereby reducing the number of read reference voltages. Hence, calibrating the integration time(s) is very efficient timewise. Also, power consumption may be reduced.


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