The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Jul. 19, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Xiaoqian Zhang, San Jose, CA (US);

Ephrem C. Wu, San Mateo, CA (US);

David Berman, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G06F 7/544 (2006.01); G06F 9/38 (2018.01); G06F 9/54 (2006.01); G06F 12/0875 (2016.01); G06N 3/04 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 7/5443 (2013.01); G06F 9/3885 (2013.01); G06F 9/545 (2013.01); G06F 12/0875 (2013.01); G06N 3/04 (2013.01);
Abstract

A circuit arrangement includes an array of MAC circuits, wherein each MAC circuit includes a cache configured for storage of a plurality of kernels. The MAC circuits are configured to receive a first set of data elements of an IFM at a first rate. The MAC circuits are configured to perform first MAC operations on the first set of the data elements and a first one of the kernels associated with a first OFM depth index during a first MAC cycle, wherein a rate of MAC cycles is faster than the first rate. The MAC circuits are configured to perform second MAC operations on the first set of the data elements and a second one of the kernels associated with a second OFM depth index during a second MAC cycle that consecutively follows the first MAC cycle.


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