The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Oct. 30, 2020
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Pradip Kar, Mountain House, CA (US);

Nithin Kumar Guggilla, Hyderabad, IN;

Chaithanya Dudha, San Jose, CA (US);

Satyaprakash Pareek, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/33 (2020.01); G06F 30/398 (2020.01); G11C 7/00 (2006.01); G11B 5/00 (2006.01); G06F 30/343 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/33 (2020.01); G06F 30/343 (2020.01); G06F 30/398 (2020.01); G11C 7/00 (2013.01);
Abstract

Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.


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