The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2022

Filed:

Dec. 18, 2019
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Hee Jin Byun, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G11C 8/10 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 13/1668 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 8/10 (2013.01);
Abstract

A semiconductor device includes first and second memory regions spaced apart from each other and a fail information storage region disposed between the first and second memory regions. A parity including error information on data is stored in a first parity region of the fail information storage region while a write operation is applied to the first memory region. The parity is stored in a second parity region of the fail information storage region while the write operation is applied to the second memory region. An error of the data is corrected by the parity stored in the first parity region while a read operation is applied to the first memory region. The error of the data is corrected by the parity stored in the second parity region while the read operation is applied to the second memory region.


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