The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2022
Filed:
Mar. 23, 2017
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Nicholas Stephen Dellas, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/40 (2006.01); H01L 29/20 (2006.01); H01L 21/28 (2006.01); H01L 23/29 (2006.01); H01L 29/51 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 21/28264 (2013.01); H01L 23/291 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01); H01L 29/401 (2013.01); H01L 29/513 (2013.01); H01L 29/66462 (2013.01); H01L 29/7781 (2013.01);
Abstract
A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is >5 A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer.