Semiconductor memory device capable of supporting asynchronous power-down mode, and operating method thereof

Abstract

According to an embodiment of the present disclosure, a semiconductor memory device includes a first buffer circuit suitable for receiving a command/address signal to output a first buffered signal according to a first control signal; a first setup/hold circuit suitable for delaying the first buffered signal to output an internal command/address signal according to a second control signal; a command decoder suitable for generating a plurality of internal signals by decoding the internal command/address signal according to a third control signal and an internal dock signal; and a timing controller suitable for delaying a dock enable signal to generate the first to third control signals, and controlling the first to third control signals to be deactivated in a first sequence when entering a power-down mode, and to be activated in a second sequence different from is the first sequence when exiting the power-down mode.