Shift register and driving method thereof, gate driving circuit and display device capabling reset the output terminal

Abstract

The present disclosure provides a shift register including: a pre-charge reset circuit and an output circuit, the pre-charge reset circuit is configured to write, in a pre-charge stage, an input signal in an active level state into the pull-up node in response to the control of a first control signal, and write, in a reset stage, an input signal in an inactive level state into the pull-up node in response to the control of a second control signal; the output circuit is configured to write, in an output stage, a clock signal in an active level state into a signal output terminal in response to the control of an electric signal in an active level state at the pull-up node, and write, in the reset stage, a clock signal in an inactive level state into the signal output terminal in response to the control of the second control signal.