The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Aug. 31, 2020
Applicant:

Siemens Industry Software Inc., Plano, TX (US);

Inventors:

Grzegorz Mrugalski, Swarzedz, PL;

Szczepan Urban, Gowarzewo, PL;

Jakub Janicki, Poznan, PL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 7/50 (2006.01); G06F 30/333 (2020.01); G01R 31/3185 (2006.01); G01R 31/28 (2006.01); G01R 31/319 (2006.01); G01R 31/3183 (2006.01); G06F 30/33 (2020.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); G01R 31/2834 (2013.01); G01R 31/31921 (2013.01); G01R 31/318357 (2013.01); G01R 31/318536 (2013.01); G01R 31/318547 (2013.01); G01R 31/318583 (2013.01); G06F 30/33 (2020.01);
Abstract

This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting. The computing system can perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains. The computing system can determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains, and generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.


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