The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Jun. 16, 2017
Applicant:

Hewlett-packard Development Company, L.p., Spring, TX (US);

Inventors:

Seung-hun Park, Suwon-si, KR;

Seob Cho, Suwon-si, KR;

Keon-young Seo, Suwon-si, KR;

Nam-jin Kim, Suwon-si, KR;

Kwang-Rae Jo, Suwon-si, KR;

Jung-Soo Park, Suwon-si, KR;

Youn-Jae Kim, Suwon-si, KR;

Jeong-Nam Cheon, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/0793 (2013.01); H05K 1/181 (2013.01); H05K 2201/10159 (2013.01);
Abstract

An electronic device is disclosed. The electronic device comprises a circuit board, a memory part comprising a plurality of first memory chips mounted on the circuit board, a socket part comprising a plurality of terminals electrically connected to a memory module which comprises a plurality of second memory chips, a memory controller for controlling the operation of the plurality of first memory chips and, when the memory module is connected to the socket part, controlling the operation of the plurality of first memory chips and the plurality of second memory chips, a conductive pattern comprising a control line which sequentially connects, from the memory controller, one or more of the plurality of terminals on the socket part and the plurality of first memory chips, and a capacitive element connected to the control line at a preset position between the one or more terminals on the socket part and the memory controller.


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