The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 23, 2022

Filed:

Feb. 22, 2021
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Kwang Su Kim, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/0873 (2016.01); G06F 13/16 (2006.01); G06F 12/0891 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0238 (2013.01); G06F 12/0873 (2013.01); G06F 12/0891 (2013.01); G06F 13/1668 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A memory system includes: a first memory subsystem suitable for storing a first segment of map data for first logical addresses in a logical address region; a second memory subsystem suitable for storing a second segment of map data for second logical addresses in the logical address region; and a host interface suitable for: providing any one of the first and second memory subsystems with a first read command of a host according to a logical address included in the read command, providing the host with an activation recommendation according to a read count of the logical address region including the provided logical address, providing map data for the first and second logical addresses obtained from the first and second memory subsystems, wherein the activation recommendation allows the host to further provide a physical address corresponding to a target logical address in the logical address region.


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